A problem area in IC chip manufacturing is achieving the dwindling feature sizes necessary to accomplish greater device densities. The meaning of the term “devices” here comprises all the desirable electrical circuit elements to which those skilled in the integrated circuit arts seek to achieve on their chips. For example, active elements like transistors and diodes, passive elements such as capacitors and resistors, or the substrates, metal wires and insulators used to connect the above into circuits. As lithography advances allow device features to shrink their dimensions horizontally, control of the feature positions and vertical dimensions becomes increasingly difficult and important. As critical dimensions continue to decrease, issues such as topography and overlay errors become more significant in determining product yield. It is therefore desirable to have methods and structures for mitigating issues caused by topography variation and overlay errors.